The present disclosure relates to semiconductor integrated circuits, and more specifically, relates to techniques for increasing accuracy of pattern dimensions of gate lines.
A gap between dimensions of lines and wavelength of exposure light is increasing as semiconductor integrated circuits become smaller. Thus, the semiconductor integrated circuits tend to be affected by diffracted light and coherent light from neighboring patterns, which results not only in poor reproduction of design patterns, but also in an increased possibility of a break or a short between neighboring patterns. Optical Proximity Correction (OPC) is known as a technique of reducing an effect of coherent light from neighboring patterns. OPC is a technique in which irregularities of line width due to space between lines are predicted, and patterns are corrected to compensate the irregularities, thereby making a final line width constant. However, the application of OPC may increase chip area because space between neighboring patterns is increased due to insertion of compensation patterns.
Patent Document 1 (U.S. Pat. No. 7,446,352) describes a technique of avoiding the effect of coherent light without using OPC. Patent Document 1 discloses a technique of configuring a logic cell by using only a one-dimensional pattern. The use of this technique does not only eliminate the need for OPC, but also allows easier application of a phase shift mask for a linear pattern. Thus, it is possible to reduce the effect of the diffracted light, and maximize contrast of a pattern.